Measurement of Antenna Radiation Pattern using Injection Locking Technique

This paper presents practical results using injection locking to synchronize the local oscillator on a wireless device enabling antenna measurements to be made in a modern anechoic chamber, overcoming the need to connect a cable to the device under tes

Benefits of active transmit balanced antenna fed by differential power amplifier

A differential amplifier feeding a balanced antenna is investigated experimentally. This approach would suit modern RFIC design rather than using a 50Ω unbalanced connection. As such the balun or power-combining network is eliminated resulting in a compact RF front-end design with wider bandwidth and lower losses. Experimental result shows that this technique promises higher output power compared to conventional feeding approach while using same RFIC and same power supply

Blind separation of convolved sources using the independent component analysis and information maximization approach

Independent Component Analysis (ICA) is very closely related to the method called blind source separation (BSS) or blind signal separation. In Independent Component Analysis (ICA) components are assumed statistically independent which we call independent source signal. In our thesis we have considered only noiseless ICA case. In a number of real-world signal processing applications, signals from various independent sources may get distorted by environmental factors that can be represented as convolutive mixtures of original signals received at the sensors. In this thesis, the effects of environmental factors and modeling assumptions on the performance capabilities of independent component analysis-based techniques are investigated. The so-called blind source separation feedback network architecture that is capable of coping with convolutive mixtures of sources is derived using Bell and Sejnowski's information maximization principle

Experimental investigation of on-site degradation of crystalline silicon PV modules under Malaysian climatic condition

Photovoltaic (PV) power plant capacity is growing very fast in Malaysia. The operating capacity of a PV plant digresses from the installed capacity after several years of operation. The degradation rate of different poly and mono crystalline silicon PV modules due to real field aging at various time spans has been detected by EL imaging, maximum power measurement and dark I-V analysis. The obtained degradation values of PV modules are 1.78, 7.06, 13.92, 17.04 and 17.42% due to ageing at a period of 8 months, 16 months, 4 years, 9 years and 11 years, respectively. The reason behind this degradation is attributed to the reduction of shunt resistance which declines gradually as result of aging. The degradation rate of a PV module has been estimated as 18.61% after 21 years of aging. Temperature coefficient of maximum power of PV module also degrades due to aging. And the rate of temperature coefficient of maximum power degradation decreases with the increase of aging period

A Wireless, High-Voltage Compliant, and Energy-Efficient Visual Intracortical Microstimulator

RÉSUMÉ L’objectif général de ce projet de recherche est la conception, la mise en oeuvre et la validation d’une interface sans fil intracorticale implantable en technologie CMOS avancée pour aider les personnes ayant une déficience visuelle. Les défis majeurs de cette recherche sont de répondre à la conformité à haute tension nécessaire à travers l’interface d’électrode-tissu (IET), augmenter la flexibilité dans la microstimulation et la surveillance multicanale, minimiser le budget de puissance pour un dispositif biomédical implantable, réduire la taille de l’implant et améliorer le taux de transmission sans fil des données. Par conséquent, nous présentons dans cette thèse un système de microstimulation intracorticale multi-puce basée sur une nouvelle architecture pour la transmission des données sans fil et le transfert de l’énergie se servant de couplages inductifs et capacitifs. Une première puce, un générateur de stimuli (SG) éconergétique, et une autre qui est un amplificateur de haute impédance se connectant au réseau de microélectrodes de l’étage de sortie. Les 4 canaux de générateurs de stimuli produisent des impulsions rectangulaires, demi-sinus (DS), plateau-sinus (PS) et autres types d’impulsions de courant à haut rendement énergétique. Le SG comporte un contrôleur de faible puissance, des convertisseurs numérique-analogiques (DAC) opérant en mode courant, générateurs multi-forme d’ondes et miroirs de courants alimentés sous 1.2 et 3.3V se servant pour l’interface entre les deux technologies utilisées. Le courant de stimulation du SG varie entre 2.32 et 220μA pour chaque canal. La deuxième puce (pilote de microélectrodes (MED)), une interface entre le SG et de l’arrangement de microélectrodes (MEA), fournit quatre niveaux différents de courant avec la valeur maximale de 400μA par entrée et 100μA par canal de sortie simultanément pour 8 à 16 sites de stimulation à travers les microélectrodes, connectés soit en configuration bipolaire ou monopolaire. Cette étage de sortie est hautement configurable et capable de délivrer une tension élevée pour satisfaire les conditions de l’interface à travers l’impédance de IET par rapport aux systèmes précédemment rapportés. Les valeurs nominales de plus grandes tensions d’alimentation sont de ±10V. La sortie de tension mesurée est conformément 10V/phase (anodique ou cathodique) pour les tensions d’alimentation spécifiées. L’incrémentation de tensions d’alimentation à ±13V permet de produire un courant de stimulation de 220μA par canal de sortie permettant d’élever la tension de sortie jusqu’au 20V par phase. Cet étage de sortie regroupe un commutateur haute tension pour interfacer une matrice des miroirs de courant (3.3V /20V), un registre à décalage de 32-bits à entrée sérielle, sortie parallèle, et un circuit dédié pour bloquer des états interdits.----------ABSTRACT The general objective of this research project is the design, implementation and validation of an implantable wireless intracortical interface in advanced CMOS technology to aid the visually impaired people. The major challenges in this research are to meet the required highvoltage compliance across electrode-tissue interface (ETI), increase lexibility in multichannel microstimulation and monitoring, minimize power budget for an implantable biomedical device, reduce the implant size, and enhance the data rate in wireless transmission. Therefore, we present in this thesis a multi-chip intracortical microstimulation system based on a novel architecture for wireless data and power transmission comprising inductive and capacitive couplings. The first chip is an energy-efficient stimuli generator (SG) and the second one is a highimpedance microelectrode array driver output-stage. The 4-channel stimuli-generator produces rectangular, half-sine (HS), plateau-sine (PS), and other types of energy-efficient current pulse. The SG is featured with low-power controller, current mode source- and sinkdigital- to-analog converters (DACs), multi-waveform generators, and 1.2V/3.3V interface current mirrors. The stimulation current per channel of the SG ranges from 2.32 to 220μA per channel. The second chip (microelectrode driver (MED)), an interface between the SG and the microelectrode array (MEA), supplies four different current levels with the maximum value of 400μA per input and 100μA per output channel. These currents can be delivered simultaneously to 8 to 16 stimulation sites through microelectrodes, connected either in bipolar or monopolar configuration. This output stage is highly-configurable and able to deliver higher compliance voltage across ETI impedance compared to previously reported designs. The nominal values of largest supply voltages are ±10V. The measured output compliance voltage is 10V/phase (anodic or cathodic) for the specified supply voltages. Increment of supply voltages to ±13V allows 220μA stimulation current per output channel enhancing the output compliance voltage up to 20V per phase. This output-stage is featured with a high-voltage switch-matrix, 3.3V/20V current mirrors, an on-chip 32-bit serial-in parallel-out shift register, and the forbidden state logic building blocks. The SG and MED chips have been designed and fabricated in IBM 0.13μm CMOS and Teledyne DALSA 0.8μm 5V/20V CMOS/DMOS technologies with silicon areas occupied by them 1.75 x 1.75mm2 and 4 x 4mm2 respectively. The measured DC power budgets consumed by low-and mid-voltage microchips are 2.56 and 2.1mW consecutively

Voted Approach for Part of Speech Tagging in Bengali

PACLIC 23 / City University of Hong Kong / 3-5 December 200